1. Field of the Invention
The present invention relates to a master slice type semiconductor integrated circuit in which various logic circuits are formed by commonly carrying out product steps except a wiring step, and changing only the wiring step.
2. Description of the Related Art
Conventionally, a semi-custom designing method is known, as a technique for designing a semiconductor integrated circuit such as LSI and the like, in a short time. In particular, this method includes a master slice method in which a master slice containing a cell having a basic level function, such as a logic gate, a flip-flop and the like, is prepared in advance, and a user then determines a wiring pattern in accordance with an individually given logic circuit and attains a desirable semiconductor integrated circuit.
FIG. 1A is a plan view showing a chip structure of the conventional master slice type semiconductor integrated circuit, and FIG. 1B is a plan view in which a transistor cell of the semiconductor integrated circuit of FIG. 1A is enlarged. A semiconductor integrated circuit 101 of the conventional master slice type has the array structure in which transistor cells 102 of the same dimension having the structure shown in FIG. 1B are arranged as a matrix on a chip. In FIG. 1B, a reference number 103 denotes a gate electrode, and a reference number 104 denotes a diffusion layer.
Also, in the conventional master slice type semiconductor integrated circuit, a clock signal is distributed to respective circuits on the chip by using a tree structure of a clock buffer referred to as a clock tree. FIG. 2 is a plan view showing a clock distributing method in the conventional master slice type semiconductor integrated circuit.
In the tree structure of the clock buffer, a clock signal CLK is distributed from a first clock buffer 105 at a center to a plurality of second clock buffers 106, and the clock signal CLK is distributed from the second clock buffer 106 to a plurality of third clock buffers 107. Moreover, the clock signal CLK is distributed from the third clock buffer 107 to a circuit 108, such as a flip-flop circuit and the like. A sequential circuit and a combinational circuit are freely placed on the chip. A clock phase number is also distributed, as necessary, by using the tree structure.
Another master slice type semiconductor integrated circuit is disclosed in Japanese Laid Open Patent Application (JP-A-Heisei 6-188397). FIG. 3 is a plan view showing a chip structure of the master slice type semiconductor integrated circuit disclosed in Japanese Laid Open Patent Application (JP-A-Heisei 6-188397). This semiconductor integrated circuit 201 has the structure in which an inner core area A is divided into a plurality of basic cell areas D by forming the inner core area A where basic cells are arranged as a matrix on a chip and further forming a cell area C dedicated to a sequential circuit. A clock buffer having high driving ability is formed in the cell area C dedicated to the sequential circuit, and the respective basic cells are formed adjacently to positions at which they can be connected at the shortest distance. Also, a combinational circuit besides the sequential circuit and the like are placed in an area E within the basic cell area D.
In the master slice type semiconductor integrated circuits shown in FIGS. 1 and 2, the sequential circuits are placed at random. Thus, the numbers of the sequential circuits connected to the respective clock buffers and the wiring lengths from the clock buffers to the sequential circuits are different, which brings about the situation that the load capacitance of the respective clock buffers and the wiring resistance until the respective sequential circuits are irregular. For this reason, the conventional semiconductor integrated circuit has a problem that a clock skew between the sequential circuits is large. In particular, if a large macro is placed, the clock wiring bypasses a macro area of the large macro. Hence, the irregular situation becomes more conspicuous. Also, since the transistor dimensions of the respective cells are equal to each other, a gate capacitance of a clock gate portion of the sequential circuit is larger than that of a block for a cell base, which results in a problem of an increase in an electric power consumption.
On the other hand, in the master slice type semiconductor integrated circuit shown in FIG. 3, the sequential circuits are collectively arranged in the dedicated area near a clock driver. Therefore, as the number of the sequential circuits is increased, the area for the sequential circuits is increased. Consequently, a distance between the nearest sequential circuit and the farthest sequential circuit is increased, which brings about a severe influence caused by a wiring resistance, which results in a problem that a clock skew between the sequential circuits becomes larger. In particular, as the size of the sequential circuits in the entire circuit becomes larger, the clock skew is increased. Also, if the number of the sequential circuits is known in advance in the custom design, the sequential circuits can be uniformly assigned to the respective clock buffers. However, if the configuration shown in FIG. 3 is applied to a design of the semi-custom semiconductor integrated circuit such as a gate array, it is difficult to uniformly assign the sequential circuits to the respective clock buffers. If the sequential circuits are excessively assigned in anticipation of a margin, load capacitance (wiring capacitance and gate capacitance) of the clock buffer is increased, which results in a problem of an increase in the electric power consumption. Also, if trying to cope with a poliphase clock, it is difficult to establish the area dedicated to the sequential circuit. Moreover, the uselessness of the electric power consumption becomes large.
As the related art, Japanese Laid Open Patent Application (JP-A-Heisei 6-244282) discloses a technique for attaining an extremely small clock skew, in a semiconductor integrated circuit apparatus having a clock synchronization circuit that is highly integrated and made into a large scale. In this semiconductor integrated circuit apparatus, a clock driver for outputting a clock signal and a plurality of grid-shaped wiring structures are connected such that their wiring lengths are equal, and a low order clock tree structure composed of slave buffers, flip-flops and the like are connected in a grid-shaped wiring structure. Consequently, it is possible to suppress even the clock skew between the grid-shaped wiring structures, simultaneously with the clock skew within the grid-shaped wiring structure. Thus, the clock skew in a large area can be reduced.
Japanese Laid Open Patent Application (JP-A-Heisei 10-308450) discloses a semiconductor integrated circuit that can cancel out a delay time difference (a skew) between flip-flops to which a clock signal of a gated clock circuit to suppress an electric power consumption of a clock line is supplied, and a method of designing the same. This semiconductor integrated circuit is the gated clock circuit having a clock tree structure constituted by a combination of a route buffer, a plurality of stages of buffers sequentially branched from the route buffer and final stage multi-input gates (NOR gates). Its connection relation is established after the arrangements of all cells. Also, after the flip-flops connected to the clock line are clustered for each function, the clustering is further carried out between the nearby flip-flops arranged in the neighborhood. Consequently, the loads, which are driven by the respective buffers and the multi-input gates, become constant. This design can cancel out the skew.
Japanese Laid Open Patent Application (JP-A-Heisei 11-111850) discloses a clock supplying circuit having a configuration that can easily reduce the clock skew, and its layout method and a semiconductor integrated circuit apparatus. The clock supplying circuit includes a first buffer element in which an input terminal is connected to a clock signal source terminal and a second buffer element in which an output terminal is connected to clock input terminals of flip-flops (FFs), and a clock signal is supplied to the respective flip-flops. The first and second buffer elements are connected to each other through a third buffer element without any branch. The third buffer element is placed at a position at which a wiring length between the first and second buffer elements is defined so as to reduce the clock skew, in view of the layout.
Also, Japanese Laid Open Patent Application (JP-A-Showa 62-4343) discloses a master slice type semiconductor integrated circuit apparatus, in which processes except a wiring process are commonly carried out, and various logic circuits are constituted by changing only the wiring step. In this master slice type semiconductor integrated circuit apparatus, the particular logic circuit is installed in the particular area of the inner cell areas constituting the various logic circuits.
Moreover, Japanese Laid Open Patent Application (JP-A 2000-294651) discloses a clock skew layout method. In this method, a plurality of local buffers are arranged around the global buffer to which a clock signal is supplied. Moreover, flip-flops constituting registers are arrayed on bars (wiring) crossing wiring extending by the same distance in a plurality of directions from the local buffer. Thus, transmission delay times can be uniformed to thereby reduce the clock skew.
The present invention is accomplished in view of the above mentioned problems. Therefore, an object of the present invention is to provide a master slice type semiconductor integrated circuit that can cope with a poliphase clock and reduce a clock skew between circuits.
Another object of the present invention is to provide a master slice type semiconductor integrated circuit that can reduce electric power consumption.
A semiconductor integrated circuit of the present invention includes sequential circuit cells (2) and combinational circuit cells (3), which are alternately arranged in an inner core area on a semiconductor chip, and a plurality of selective driving elements (MC101 to MC108, MC201 to MC216 and MC301 to MC316), which are connected in a shape of a tree, for selectively distributing a poliphase clock signal for each division area after the inner core area is uniformly divided. The plurality of selective driving elements (MC101 to MC108, MC201 to MC216 and MC301 to MC316) are placed and connected on the semiconductor chip (1) such that load and wiring length between the sequential circuit cells (2) within the respective division areas and input terminals to which the poliphase clock signal is inputted are equal to each other.
Also, in one configuration example of the semiconductor integrated circuit in the present invention, the sequential circuit cell includes: a first logical gate element (INV2) placed at a first stage of a clock input portion to which the poliphase clock signal is inputted; and a second logical gate element (INV3) placed immediately after this first logical gate element, and wherein for a sequential circuit cell to be used in the sequential circuit cells, a wiring for a connection is laid between an output terminal of the first logical gate element and an input terminal of the second logical gate element, and for a sequential circuit cell to be not used in the sequential circuit cells, the wiring is not laid between the output terminal of the first logical gate element and the input terminal of the second logical gate element, and the input terminal of the second logical gate element is connected to a power supply or a ground.
Also, in one configuration example of the semiconductor integrated circuit in the present invention, the sequential circuit cell includes: a first logical gate element (NAND1), which is placed at the first stage of the clock input portion to which the poliphase clock signal is inputted, for enabling a first state at which an output potential is determined based on the poliphase clock signal or a second state at which the output potential is constant irrespectively of the poliphase clock signal to be selected through an enable signal; and a second logical gate element (INV3) in which an input terminal is connected to an output terminal of the first logical gate element, and wherein for a sequential circuit cell to be used in the sequential circuit cells, the enable signal is set such that the first logical gate element becomes at the first state, and for a sequential circuit cell to be not used in the sequential circuit cells, the enable signal is set such that the first logical gate element becomes at the second state.
Also, in one configuration example of the semiconductor integrated circuit in the present invention, when the sequential circuit cell placed in the each division area to which the poliphase clock signal is distributed by one selective driving element of the plurality of selective driving elements, or the sequential circuit cell placed in the division area to which the poliphase clock signal is distributed by the one selective driving element through a different selective driving element is not used, an output of the one selective driving element is prevented.
A layout method of a semiconductor integrated circuit in the present invention includes the steps of: arranging sequential circuit cells and combinational circuit cells in an inner core area on a semiconductor chip; and arranging and connecting, in a shape of a tree, a plurality of selective driving elements for selectively distributing a poliphase clock signal for each division area formed by uniformly dividing said inner core area, wherein the plurality of selective driving elements are arranged and connected on the semiconductor chip such that load and wiring length between the sequential circuit cells within the respective division areas from input terminals to which the poliphase clock signal is inputted are equal to each other.
Also, in one configuration example of a layout method of a semiconductor integrated circuit in the present invention, wherein each of the sequential circuit cell is formed at a situation that a wiring is not laid between a first logical gate element placed at a first stage of a clock input to which the poliphase clock signal is inputted and a second logical gate element placed immediately after this first logical gate element, and wherein for a sequential circuit cell to be used in the sequential circuit cells, an output terminal of the first logical gate element and an input terminal of the second logical gate element are connected to each other at an arrangement wiring step, and for a sequential circuit cell to be not used in the sequential circuit cells, the wiring is not laid between the output terminal of the first logical gate element and the input terminal of the second logical gate element, and the input terminal of the second logical gate element is wired and connected to a power supply or a ground at the arrangement wiring step.
Also, in one configuration example of a layout method of a semiconductor integrated circuit in the present invention, the sequential circuit cell includes: a first logical gate element, which is placed at the first stage of the clock input to which the poliphase clock signal is inputted, for enabling a first state at which an output potential is determined on the basis of the poliphase clock signal or a second state at which the output potential is constant irrespectively of the poliphase clock signal to be selected through an enable signal; and a second logical gate element in which an input terminal is connected to an output terminal of the first logical gate element, and wherein for a sequential circuit cell to be used in the sequential circuit cells, a value of the enable signal is set such that the first logical gate element becomes at the first state, in an arrangement wiring step, and for a sequential circuit cell to be not used in the sequential circuit cells, a value of the enable signal is set such that the first logical gate element becomes at the second state, in the arrangement wiring step.
Also, in one configuration example of a layout method of a semiconductor integrated circuit in the present invention, when the sequential circuit cell placed in the division area to which the poliphase clock signal is distributed by one selective driving element of the plurality of selective driving elements, or the sequential circuit cell placed in the division area to which the poliphase clock signal is distributed by the one selective driving element through a different selective driving element is not used, an output of the one selective driving element is prevented.